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60 mhz, g = +2, 16 16 buffered analog crosspoint switch data sheet ADV3205 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 16 16 high speed nonblocking switch array serial or parallel programming of switch array serial data out allows daisy-chaining control of multiple 16 16 devices to create larger switch arrays complete solution buffered inputs 16 output amplifiers operates on 5 v supplies low supply current of 50 ma excellent video performance, v s = 5 v ?3 db bandwidth: 60 mhz 0.1 db gain flatness: 10 mhz 0.1% differential gain error (r l = 1 k) 0.1 differential phase error (r l = 1 k) low all hostile crosstalk: ?67 db at 5 mhz output disable allows connection of multiple devices without loading the output bus reset pin allows disabling of all outputs power-on reset capability with capacitor to ground 100-lead lqfp (14 mm 14 mm) applications cctv surveillance video routers (ntsc, pal, s-video, secam) video conferencing functional block diagram ADV3205 output buffer g = +2 80 80 256 80-bit shift register with 5-bit parallel loading parallel latch decode 16 5:16 decoders 16 clk data in update ce reset 16 inputs a0 data out 16 outputs set individual or reset all outputs to ?off? a1 a2 ser/par d0 d1 d2 d3 d4 enable/disable a3 switch matrix 10342-001 figure 1. general description the ADV3205 is a fully buffered crosspoint switch matrix that operates on 5 v, making it ideal for video applications. it offers a ?3 db signal bandwidth of 60 mhz and channel switch times of less than 60 ns with 0.1% settling. the ADV3205 has excellent crosstalk performance, and ground/power pins surround all inputs and outputs to provide extra shielding required for the most demanding applications. the differential gain and differential phase of better than 0.1% and 0.1, respectively, along with 0.1 db flatness out to 10 mhz, make the ADV3205 an excellent choice for many video applications. the ADV3205 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs. the ADV3205 has a gain of +2 and operates on voltage supplies of 5 v while consuming only 34 ma of current. channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array. the ADV3205 is packaged in a 100-lead lqfp and is available over the commercial temperature range of 0c to 70c.
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ADV3205 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? timing characteristics (serial mode) ....................................... 4 ? timing characteristics (parallel mode) .................................... 5 ? absolute maximum ratings............................................................ 6 ? power dissipation......................................................................... 6 ? esd caution.................................................................................. 6 ? pin configuration and function descriptions............................. 7 ? truth table and logic diagram ................................................. 9 ? typical performance characteristics ........................................... 10 ? circuit diagrams ............................................................................ 13 ? theory of operation ...................................................................... 14 ? short-circuit output conditions............................................. 14 ? applications information .............................................................. 15 ? serial programming ................................................................... 15 ? parallel programming................................................................ 15 ? power-on reset.......................................................................... 16 ? managing video signals............................................................ 16 ? creating larger crosspoint arrays.......................................... 16 ? multichannel video ................................................................... 17 ? crosstalk ...................................................................................... 17 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 12/11revision 0: initial version
data sheet ADV3205 rev. 0 | page 3 of 20 specifications t a = 25c, v s = 5 v, r l = 150 , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth v out = 200 mv p-p 41 60 mhz v out = 2 v p-p 25 mhz gain flatness 0.1 db, v out = 200 mv p-p 10 mhz propagation delay v out = 2 v p-p 20 ns settling time 0.1%, 2 v output step 23 ns slew rate 2 v output step 100 v/s noise/distortion performance differential gain error ntsc, r l = 1 k 0.1 % differential phase error ntsc, r l = 1 k 0.1 degrees crosstalk, all hostile f = 5 mhz ?67 db off isolation f = 5 mhz, one channel ?100 db input voltage noise 0.1 mhz to 10 mhz 12 nv/hz dc performance gain error 0.5 % gain matching channel-to-channel 0.7 % gain temperature coefficient 20 ppm/c output characteristics output resistance enabled 0.3 disabled 3.4 4 k output capacitance disabled 5 pf output voltage swing no load 3.2 3.5 v i out = 20 ma 2.7 3 v short-circuit current 55 ma input characteristics input offset voltage all configurations 5 10 mv temperature coefficient 10 v/c input voltage range no load 1.5 v input capacitance any switch configuration 4 pf input resistance any number of connected outputs 50 m input bias current any number of enabled inputs 1 a switching characteristics enable on time 80 ns switching time, 2 v step 50% up date to 1% settling 50 ns switching transient (glitch) 20 mv p-p power supplies supply current av cc outputs enabled, no load 45 50 ma av cc outputs disabled 31 35 ma av ee outputs enabled, no load 45 50 ma av ee outputs disabled 31 35 ma dv cc outputs enabled, no load 8 13 ma dynamic performance supply voltage range av cc 4.5 5.5 v av ee ?5.5 ?4.5 v dv cc 4.5 5.5 v psrr dc 75 80 db f = 100 khz 60 db f = 1 mhz 40 db
ADV3205 data sheet rev. 0 | page 4 of 20 parameter test conditions/comments min typ max unit operating temperature range temperature range operating (still air) 0 70 c ja operating (still air) 40 c/w timing characteristics (serial mode) table 2. limit parameter symbol min typ max unit serial data setup time t 1 20 ns clk pulse width t 2 100 ns serial data hold time t 3 20 ns clk pulse separation, serial mode t 4 100 ns clk-to- update delay t 5 0 ns update pulse width t 6 50 ns clk-to-data out valid, serial mode t 7 200 ns propagation delay, update to switch on or off 50 ns data load time, clk = 5 mhz, serial mode 16 s clk, update rise and fall times 100 ns reset time 200 ns load data into serial register on falling edge 1 0 1 0 data in clk 1 = latched 0 = transparen t data out out07 (d4) out07 (d3) out00 (d0) transfer data from serial register to parallel latches during low level t 7 t 1 t 3 t 6 t 2 t 4 t 5 update 10342-002 figure 2. timing diagram, serial mode table 3. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par clk, data in, ce , update reset , ser /par clk, data in, ce , update data out data out reset , ser /par clk, data in, ce , update reset , ser /par clk, data in, ce , update data out data out 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?400 a max 3.0 ma min
data sheet ADV3205 rev. 0 | page 5 of 20 timing characteristics (parallel mode) table 4. limit parameter symbol min max unit parallel data setup time t 1d 20 ns address setup time t 1a 20 ns clk enable width t 2 100 ns parallel data hold time t 3d 20 ns address hold time t 3a 20 ns clk pulse separation t 4 100 ns clk-to- update delay t 5 0 ns update pulse width t 6 50 ns propagation delay, update to switch on or off 50 ns clk, update rise and fall times 100 ns reset time 200 ns 10342-003 1 0 clk 1 0 a0 to a3 1 0 d0 to d4 1 = latched update 0 = transparen t t 6 t 5 t 1a t 3a t 3d t 1d t 4 t 2 figure 3. timing diagram, parallel mode table 5. logic levels v ih v il v oh v ol i ih i il i oh i ol reset , ser /par clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update reset , ser /par clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update data out data out reset , ser /par clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update reset , ser /par clk, d0, d1, d2, d3, d4, a0, a1, a2, a3, ce , update data out data out 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max ?400 a min ?400 a max 3.0 ma min
ADV3205 data sheet rev. 0 | page 6 of 20 absolute maximum ratings power dissipation table 6. parameter rating analog supply voltage (av cc to av ee ) 12 v digital supply voltage (dv cc to dgnd) 6 v ground potential difference (agnd to dgnd) 0.5 v internal power dissipation 1 3.1 w analog input voltage 2 maintain linear output digital input voltage dv cc output voltage (disabled output) (av cc ? 1.5 v) to (av ee + 1.5 v) output short-circuit duration momentary storage temperature range ?65c to +125c lead temperature (soldering 10 sec) 300c packaged in a 100-lead lqfp, the ADV3205 junction-to-ambient thermal impedance ( ja ) is 40c/w. for long-term reliability, the maximum allowed junction temperature of the plastic encapsulated die should not exceed 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. the maximum ADV3205 power dissipation occurs when all outputs are enabled and driving loads. supply current increases approximately linearly with the number of outputs that are enabled. refer to the theory of operation section for more details regarding power dissipation calculations. figure 4 indicates the maximum ADV3205 power dissipation as a function of ambient temperature. 1 specification is for device in free air (t a = 25c): 100-lead plastic lqfp: ja = 40c/w. 2 to avoid differential input breakdown, in no case should one-half the output voltage (1/2 v out ) and any input voltage be greater than 10 v potential differential. see the output voltage swing parameter in table 1 for the linear output range. t j = 150c ambient temperature (c) maximum power (w) 4.0 3.5 3.0 2.5 2.0 10 0 20304050607 10342-004 0 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 4. maximum power dissipation vs. ambient temperature esd caution
data sheet ADV3205 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions 10342-006 nc = no connect reset ce data out clk data in update ser/par nc nc nc nc nc nc nc nc nc a0 a1 a2 a3 d0 d1 d2 d3 d4 26 av cc 13/14 27 out13 28 av ee 12/13 29 out12 30 av cc 11/12 31 out11 32 av ee 10/11 33 out10 34 av cc 09/10 35 out09 36 av ee 08/09 37 out08 38 av cc 07/08 39 out07 2 dgnd 3 agnd 4 in08 7 agnd 6 in09 5 agnd 1 dv cc 8 in10 9 agnd 10 in11 12 in12 13 agnd 14 in13 15 agnd 16 in14 17 agnd 18 in15 19 agnd 20 av ee 21 av cc 22 av cc 15 23 out15 24 av ee 14/15 25 out14 11 agnd 74 dgnd dv cc 73 agnd 72 in07 69 agnd 70 in06 71 agnd 75 68 in05 67 agnd 66 in04 64 in03 63 agnd 62 in02 61 agnd 60 in01 59 agnd 58 in00 57 agnd 56 av ee 55 av cc 54 av cc 00 53 out00 52 av ee 00/01 51 out01 65 agnd 40 av ee 06/07 41 out06 42 av cc 05/06 43 out05 44 av ee 04/05 45 out04 46 av cc 03/04 47 out03 48 av ee 02/03 49 out02 50 av cc 01/02 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 ADV3205 top view (not to scale) figure 5. pin configuration table 7. pin function descriptions pin uber neonic description 1, 75 dv cc 5 v for digital circuitry. 2, 74 dgnd ground for digital circuitry. 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63, 65, 67, 69, 71, 73 agnd analog ground for inputs and switch matrix. 4, 6, 8, 10, 12, 14, 16, 18, 58, 60, 62, 64, 66, 68, 70, 72 inxx analog inputs; xx = channel nu mber 00 through channel number 15. 20, 56 av ee ?5 v for inputs and switch matrix. 21, 55 av cc 5 v for inputs and switch matrix. 22, 54 av cc xx 5 v for output amplifier that is used by channel number xx. 26, 30, 34, 38, 42, 46, 50 av cc xx/yy 5 v for output amplifier that is shared by channel number xx and channel number yy. 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53 outyy analog outputs; yy = channel number 00 through channel number 15. 24, 28, 32, 36, 40, 44, 48, 52 av ee xx/yy ?5 v for output amplifier that is shared by channel number xx and channel number yy. 76 d4 parallel data input, ttl compatible (output enable). 77 d3 parallel data input, tt l compatible (input select msb). 78 d2 parallel data input, ttl compatible (input select). 79 d1 parallel data input, ttl compatible (input select).
ADV3205 data sheet rev. 0 | page 8 of 20 pin number mnemonic description 80 d0 parallel data input, tt l compatible (input select lsb). 81 a3 parallel data input, ttl compatible (output select msb). 82 a2 parallel data input, ttl compatible (output select). 83 a1 parallel data input, ttl compatible (output select). 84 a0 parallel data input, tt l compatible (output select lsb). 85 to 93 nc no connect. do not connect to this pin. 94 ser /par selects serial data mode, low or parallel data mode, high. 95 update enable (transparent) low. allows serial register to connect directly to switch matrix. data latched when high. 96 data in serial data input, ttl compatible. 97 clk clock, ttl compatible. falling edge triggered. 98 data out serial data out, ttl compatible. 99 ce chip enable, enable low. must be low to clock in and latch data. 100 reset disable outputs, active low.
data sheet ADV3205 rev. 0 | page 9 of 20 truth table and logic diagram table 8. operation truth table 1 ce update clk data in data out reset ser /par operation/comment 1 x x x x x x no change in logic. 0 1 2 data i data i-80 1 0 the data on the serial data in line is loaded into the serial register. the first bit clocked into the serial register appears at data out 80 clocks later. 0 1 3 d0 ... d4, a0 ... a3 not applicable in parallel mode 1 1 the data on the parallel data lines, d0 to d4, are loaded into the 80-bit serial shift register location addressed by a0 to a3. 0 0 x x x 1 x data in the 80-bit shift register transfers into the parallel latches that control the switch array. latches are transparent. x x x x x 0 x asynchronous operation. all outputs are disabled. remainder of logic is unchanged. 1 x = dont care, 0 = logic low, 1 = logic high, and = falling edge triggered. 2 = falling edge triggered. 3 = low level triggered. d clk q 4 to 16 decoder a0 a1 a2 clk 16 256 data in (serial) (output enable) ser/par ce update out00 en data out parallel data d q clk d q clk d q clk d q clk d1 d2 d3 d q clk d q clk d q clk d q clk d q clk out01 en out02 en out03 en out04 en out05 en out06 en out07 en d le q clr out15 en output enable switch matrix s d1 q d0 d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 s d1 q d0 d q clk s d1 q d0 d4 decode d le q clr out00 en d le out00 b0 q d le q out00 b1 d le q out00 b2 d le q out00 b3 d le out01 b0 q d le q clr out14 en d le out15 b0 q d le out15 b1 q d le out15 b2 q d q clk s d1 q d0 s d1 q d0 d le out15 b3 q s d1 q d0 out08 en out09 en out10 en out11 en out12 en out13 en out14 en out15 en a3 output address reset (output enable) 10342-005 figure 6. logic diagram
ADV3205 data sheet rev. 0 | page 10 of 20 typical performance characteristics t a = 25c, v s = 5 v, r l = 150 , unless otherwise noted. frequency (mhz) ?6 ?3 0 gain (db) 3 0.01 0.1 1 10 100 10342-012 0.1 1 10 100 frequency (mhz) ?6 ?3 0 gain (db) 3 10342-015 figure 7. small si gnal bandwidth, v out = 200 mv p-p figure 10. large signal bandwidth, v out = 2 v p-p frequency (mhz) ?0.3 ?0.1 0.1 gain flatness (db) 0.3 ?0.2 0 0.2 0.1 1 10 100 10342-016 frequency (mhz) ?0.3 ?0.1 0.1 gain flatness (db) 0.3 ?0.2 0 0.2 0.1 1 10 100 10342-013 figure 11. large signal gain flatness, v out = 2 v p-p figure 8. small signal gain flatness, v out = 200 mv p-p 0.001 0.01 0.1 1 100 10 frequency (mhz) ?110 ?100 ?80 ?60 crosstalk (db) ? 50 ?90 ?70 10342-017 second harmonic third harmonic frequency (mhz) ?100 ?80 ?60 crosstalk (db) ? 40 ?90 ?70 ?50 0.1 1 10 100 10342-014 all hostile adjacent figure 9. crosstalk vs. frequency, v out = 2 v p-p figure 12. distortion vs. frequency, v out = 2 v p-p
data sheet ADV3205 rev. 0 | page 11 of 20 frequency (mhz) ?90 ?70 ?30 psrr (db) 0 ?80 ?50 ?10 ?40 ?60 ?20 0.01 0.1 1 10 10342-018 +psrr ?psrr figure 13. psrr vs. frequency frequency (mhz) impedance ( ? ) 1k 100 10 1 0.1 0.1 1 10 100 1k 10342-019 figure 14. enabled output impedance vs. frequency frequency (mhz) ?120 ?80 ?40 off isolation (db) 0 ?100 ?60 ?20 0.1 1 10 100 10342-020 figure 15. off isolat ion vs. frequency, v out = 2 v p-p frequency (hz) 0 40 120 noise (nv hz) 160 20 80 100 60 140 10 100 1k 10k 1m 100k 10m 10342-021 figure 16. noise vs. frequency frequency (mhz) impedance ( ? ) 10k 1k 100 10 1 0.1 1 10 100 1k 10342-022 figure 17. disabled output impedance vs. frequency 051052025 5ns/div 0.1%/di v 30 35 40 45 50 output 2 ? input output input 10342-023 figure 18. settling time to 0.1%, 2 v output step
ADV3205 data sheet rev. 0 | page 12 of 20 5ns/div 50mv/div 10342-024 100ns/div 500mv/div 10342-027 figure 19. small signal pulse response figure 22. large signal pulse response 100ns/div 2v/div 10342-025 input 1 input 0 v out update 100ns/div 1v/div 20mv/div 10342-028 output update figure 23. switching transient figure 20. switching time series resistance ( ? ) 0 300 250 200 150 100 50 0 5 101520253035 c load (pf) 10342-026 figure 21. c load vs. series resistance for less than 30% overshoot
data sheet ADV3205 rev. 0 | page 13 of 20 circuit diagrams esd esd input av cc av ee 10342-007 figure 24. analog input esd esd output av cc av ee 10342-008 figure 25. analog output esd esd dv cc reset 20k ? dgnd 10342-009 figure 26. reset input esd esd input dv cc dgnd 10342-010 figure 27. logic input esd esd output dv cc dgnd 2k ? 10342-011 figure 28. logic output
ADV3205 data sheet rev. 0 | page 14 of 20 theory of operation the ADV3205 is a gain-of-two crosspoint array with 16 outputs, each of which can be connected to any one of 16 inputs. organized by output row, 16 switchable transconductance stages are connected to each output buffer in the form of a 16-to-1 multiplexer. each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins, for a total array of 256 transconductance stages. decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. the transconductance stages are npn input differential pairs, sourcing current into the folded cascode output stage. the compensation networks and emitter follower output buffers are in the output stage. voltage feedback sets the gain at +2. the ADV3205 can drive reverse-terminated video loads, swinging 3.0 v into 150 . disabling unused outputs and transconductance stages minimizes on-chip power consumption. features of the ADV3205 facilitate the construction of larger switch matrices. the unused outputs can be disabled, leaving only a feedback network resistance of 4 k on the output. this allows multiple ics to be bused together, provided the output load impedance is greater than the minimum allowed values. because no additional input buffering is necessary, high input resistance and low input capacitance are easily achieved without additional signal degradation. the ADV3205 inputs have a unique bias current compensation scheme that overcomes a problem common to transconductance input array architectures. typically, input bias current increases as more and more transconductance stages connected to the same input are turned on. anywhere from 0 to 16 transconductance stages can be sharing one input pin, so there is a varying amount of bias current supplied through the source impedance driving the input. the ADV3205 samples and cancels the input bias current contributions from each transconductance stage so that the residual bias current is nominally zero, regardless of the number of enabled inputs. the ADV3205 contains internal crosstalk isolation clamps that have variable bias levels. these levels were chosen to allow the necessary input range to accommodate the full output swing with a gain of +2. overdriving the inputs beyond the linear range of the device eventually forward biases these clamps, increasing the power dissipation. the valid input range is 1.5 v. when outputs are disabled and being driven externally, the voltage applied to them should not exceed the valid input swing range for the ADV3205 . a flexible ttl-compatible logic interface simplifies the programming of the matrix. either parallel or serial loading into a first rank of latches programs each output. a global latch simultaneously updates all outputs. in serial mode, a serial data out pin (data out) allows devices to be daisy chained together for single pin programming of multiple ics. a power-on reset function can be implemented to avoid bus conflicts by disabling all outputs. the digital logic requires 5 v on the dv cc pin with respect to dgnd. internal esd protection diodes require that the dgnd and agnd pins be at the same potential. short-circuit output conditions although there is short-circuit current protection on the ADV3205 outputs, the short-circuit output current can reach levels that can result in device failure. do not operate the ADV3205 with a sustained short to ground on any of its outputs.
data sheet ADV3205 rev. 0 | page 15 of 20 applications information the ADV3205 has two options for changing the programming of the crosspoint matrix. in the first option, a serial word of 80 bits can be provided that updates the entire matrix in one serial operation. the second option allows for changing the programming of a single output via a parallel interface. the serial option requires fewer signals but more time (clock cycles) for changing the programming, whereas the parallel programming technique requires more signals, but can change a single output at a time, and requires fewer clock cycles to complete programming. serial programming the serial programming mode uses the device pins: ce , clk, data in, update , and ser /par. the first step is to assert a low on ser /par to enable the serial programming mode. ce for the chip must be low to allow data to be clocked into the device. the ce signal can be used to address an individual device when devices are connected in parallel. the update signal should be high during the time that data is shifted into the serial port of the device. although the data still shifts in when update is low, the transparent, asynchronous latches allow the shifting data to reach the matrix. this causes the matrix to try to update to every intermediate state as defined by the shifting data. the data at data in is clocked in at every down edge of clk. a total of 80 bits must be shifted into the shift register via the data in input to complete the programming. for each of the 16 outputs, there are four bits (d0 to d3) that determine the source of its input followed by one bit (d4) that determines the enabled state of the output. if d4 is low (output disabled), the four associated bits (d0 to d3) do not matter because no input is switched to that output. the most significant output address data is shifted into the shift register first, following in sequence until the least significant output address data is shifted in. at this point update can be taken low, which causes the programming of the device according to the data that was just shifted in. the update registers are asynchronous, and when update is low (and ce is low), the registers are transparent. when more than one ADV3205 device is serially programmed in a system, the data out signal from one device can be connected to the data in of the next device to form a serial chain. connect all of the clk, ce , update , and ser /par pins in parallel and operate them as previously described. the serial data is input to the data in pin of the first device of the chain, and it ripples through to the last. therefore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the programming sequence is 80 bits times the number of devices in the chain. parallel programming when using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. in fact, parallel programming allows for the modification of a single output at a time. because this takes only one clk/ update cycle, significant time savings can be realized by using parallel programming. one important consideration in using parallel programming is that the reset signal does not reset all registers in the . when taken low, the ADV3205 reset signal only sets each output to the disabled state. this is helpful during power-up to ensure that two parallel outputs are not active at the same time. after initial power-up, the internal registers in the device generally contain random data, even though the reset signal has been asserted. if parallel programming is used to program one output, that output is properly programmed but the rest of the device has a random program state depending on the internal register content at power-up. therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. this ensures that the programming matrix is always in a known state. from then on, parallel programming can be used to modify a single output at a time. in similar fashion, if both ce and update are taken low after initial power-up, the random power-up data in the shift register is programmed into the matrix. therefore, to prevent the crosspoint from being programmed into an unknown state, do not apply low logic levels to both ce and update after power is initially applied. programming the full shift register one time to a desired state, by either serial or parallel programming after initial power-up, eliminates the possibility of programming the matrix to an unknown state. to change the outputs programming via parallel programming, take ser /par and update high and take ce low. the clk signal should be in the high state. put the 4-bit address of the output to be programmed on the a0 to a3 pins. the first four data bits (d0 to d3) should contain the information that identifies the input that is programmed to the output that is addressed. the fifth data bit (d4) determines the enabled state of the output. if d4 is low (output disabled), the data on d0 to d3 does not matter. after the desired address and data signals are established, they can be latched into the shift register by a high-to-low transition of the clk signal. the matrix is not programmed, however, until the update signal is taken low. it is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of clk while update is held high and then have all of the new data take effect when update goes low. use this technique when programming the device for the first time after power-up when using parallel programming.
ADV3205 data sheet rev. 0 | page 16 of 20 power-on reset when powering up the ADV3205 , it is usually desirable to have the outputs start up in the disabled state. the reset pin, when taken low, causes all outputs to be in the disabled state. however, the reset signal does not reset all registers in the . this is important when operating in parallel programming mode. refer to the section for information about programming internal registers after power-up. serial programming programs the entire matrix each time; therefore, no special considerations apply. ADV3205 parallel programming because the data in the shift register is random after power-up, do not use it to program the matrix or the matrix can enter unknown states. to prevent this, do not apply logic low signals to both ce and update initially after power-up. first, load the shift register with the desired data, and then take update low to program the device. the reset pin has a 20 k pull-up resistor to dv cc that can be used to create a simple power-up reset circuit. a capacitor from reset to ground holds reset low for some time while the rest of the device stabilizes. the low condition causes all outputs to be disabled. the capacitor then charges through the pull-up resistor to the high state, thus allowing full programming capability of the device. managing video signals video signals often use controlled impedance transmission lines that are terminated in their characteristic impedance. although this is not always the case, there are some considerations when using the ADV3205 to route video signals with controlled impedance transmission lines. figure 29 shows a schematic of an input and output treatment of a typical video channel. 75 ? 75? 75? 75? transmission line typical output +5 v ADV3205 g = 2 ?5v typical input 75? video source 10342-031 figure 29. video signal circuit video signals most often use 75 transmission lines that need to be terminated with this value of resistance at each end. when such a source is delivered to one of the ADV3205 inputs, the high input impedance does not properly terminate these signals. therefore, terminate the line with a 75 shunt resistor to ground. because video signals are limited in their peak-to-peak amplitude (typically no more than 1.5 v p-p), there is no need to attenuate video signals before they pass through the ADV3205 . the ADV3205 outputs are low impedance and do not properly terminate the source end of a 75 transmission line. in these cases, insert a series 75 resistor at an output that drives a video signal. then terminate the 75 transmission line with 75 at its far end. this overall termination scheme divides the amplitude of the ADV3205 output by two. an overall unity-gain channel is produced because of the channel gain-of-two of the ADV3205 . creating larger crosspoint arrays the ADV3205 is a high density building block for creating crosspoint arrays of dimensions larger than 16 16. various features, such as output disable and chip enable, are useful for creating larger arrays. the first consideration in constructing a larger crosspoint is to determine the minimum number of devices that are required. the 16 16 architecture of the ADV3205 contains 256 points, which is a factor of 64 greater than a 4 1 crosspoint (or multiplexer). the printed circuit board (pcb) area, power consumption, and design effort savings are readily apparent when compared to using these smaller devices. for a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs. some nonblocking crosspoint architectures require more than this minimum as previously calculated. in addition, there are blocking architectures that can be constructed with fewer devices than this minimum. these systems have connectivity available on a statistical basis that is determined when designing the overall system. the basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-or the outputs together in the vertical direction. the meaning of horizontal and vertical can best be understood by looking at a diagram. figure 30 illustrates this concept for a 32 32 crosspoint array that uses four ADV3205 devices. note that the 75 source terminations are not shown on the outputs, but they are required when driving the 75 transmission lines. ADV3205 ADV3205 in00 to in15 in16 to in31 ADV3205 ADV3205 16 16 16 16 75 ? 75 ? 16 16 16 8 16 16 10342-032 figure 30. 32 32 crosspoint array using four ADV3205 devices
data sheet ADV3205 rev. 0 | page 17 of 20 the inputs are individually assigned to each of the 32 inputs of the two devices, and the shunt 75 terminations are placed at the end of the transmission lines. the outputs are wire-ored together in pairs. only enable one of the outputs from a wire- ored pair at any given time. the device programming software must be properly written to achieve this. multichannel video the good video specifications of the ADV3205 make it an ideal candidate for creating composite video crosspoint switches. these switches can be made quite dense by taking advantage of the high level of integration of the ADV3205 and the fact that composite video requires only one crosspoint channel per system video channel. there are, however, other video formats that can be routed with the ADV3205 , requiring more than one crosspoint channel per video channel. some systems use twisted pair wiring to carry video signals. these systems use differential signals and can lower costs because they use lower cost cables, connectors, and termination methods. they also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment that operates in noisy environments, or where common-mode voltages are present between transmitting and receiving equipment. in such systems, the video signals are differential; there are positive and negative (or inverted) versions of the signals. these complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first-order zero common- mode voltage. at the receive end, the signals are differentially received and converted back into a single-ended signal. when switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. for a single ADV3205 , eight differential video channels can be assigned to the 16 inputs and 16 outputs. this effectively forms an 8 8 differential crosspoint switch. programming such a device requires that the inputs and outputs be programmed in pairs. this information can be deduced through inspection of the programming format of the ADV3205 and the requirements of the system. there are other analog video formats requiring more than one analog circuit per video channel. one two-circuit format that is commonly being used in video systems is s-video or y/c video. the y/c video format carries the brightness (luminance or y) portion of the video signal on one channel and the color (chrominance, chroma, or c) on a second channel. because s-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels, as in the case of a differential video system. aside from the nature of the video format, other aspects of these two systems are the same. there are yet other video formats using three channels to carry the video information. video cameras produce rgb (red, green, and blue) directly from the image sensors. rgb is also the usual format used by computers internally for graphics. rgb can also be converted to y, rCy, and bCy format, sometimes called yuv format. these three circuit video standards are referred to as analog component video. the analog component video standards require three crosspoint channels per video channel to handle the switching function. in a fashion similar to the two circuit video formats, the inputs and outputs are assigned in groups of three, and the appropriate logic programming is performed to route the video signals. crosstalk many video systems have strict requirements for keeping the various signals from influencing any of the others in the system. crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. when there are many signals in proximity in a system, as is the case in a system that uses the ADV3205 , the crosstalk issues can be quite complex. a good understanding of the nature of crosstalk and some definition of terms is required to specify a system that uses one or more ADV3205 devices. types of crosstalk crosstalk can be propagated by means of any of three methods. these fall into the categories of electric field, magnetic field, and sharing of common impedances. this section explains these effects. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (for example, free space) and couples with the receiver and induces a voltage. this voltage is an unwanted crosstalk signal in any channel that receives it. currents flowing in conductors create magnetic fields that circulate around the currents. these magnetic fields then generate voltages in any other conductors with whose paths they link. the undesired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. the power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. all these sources of crosstalk are vector quantities; therefore, the magnitudes cannot simply be added together to obtain the total crosstalk. in fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk.
ADV3205 data sheet rev. 0 | page 18 of 20 areas of crosstalk a practical ADV3205 circuit must be mounted to some sort of circuit board to connect it to power supplies and measurement equipment. this, however, raises the issue that the crosstalk of a system is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. it is important to try to separate these two areas when attempting to minimize the effect of crosstalk. in addition, crosstalk can occur among the inputs to a cross- point and among the outputs. it can also occur from input to output. techniques are presented in the following sections for diagnosing which part of a system is contributing to crosstalk, as well as minimizing crosstalk. measuring crosstalk crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. the measurement is usually expressed as db down from the magnitude of the test signal. the crosstalk is expressed by | xt | = 20log 10 ( asel(s) / atest(s) ) where: s = jw , the laplace transform variable. asel(s) is the amplitude of the crosstalk induced signal in the selected channel. atest(s) is the amplitude of the test signal. it can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to the first order). in addition, the crosstalk signal has a phase relative to the test signal associated with it. a network analyzer is most commonly used to measure crosstalk over a frequency range of interest. it can provide both magnitude and phase information about the crosstalk signal. as a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. for example, in the case of the 16 16 matrix of the ADV3205 , note the number of crosstalk terms that can be considered for a single channel, such as the in00 input. in00 is programmed to connect to one of the ADV3205 outputs where the measurement can be made. first, the crosstalk terms associated with driving a test signal into each of the other 15 inputs can be measured one at a time, while applying no signal to in00. then, the crosstalk terms associated with driving a parallel test signal into all 15 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until finally, there is only one way to drive a test signal into all 15 other inputs in parallel. each of these cases is legitimately different from the others and may yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. in addition, this describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other input. in addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers grow impractically large. if a larger crosspoint array of multiple ADV3205 devices is constructed, the numbers grow larger still. clearly, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. one common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. in general, this yields the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. other useful crosstalk measurements are those that are created by one nearest neighbor or by the two nearest neighbors on either side. these crosstalk measurements are generally higher than those of more distant channels, so they can serve as a worst-case measure for any other 1-channel or 2-channel crosstalk measurements. input and output crosstalk the flexible programming capability of the ADV3205 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. some examples are illustrative. a given input channel (in07 in the middle for this example) can be programmed to drive out07 (also in the middle). the input to in07 is just terminated to ground (via 50 or 75 ) and no signal is applied. all the other inputs are driven in parallel with the same test signal (provided by a distribution amplifier), with all other outputs except out07 disabled. because grounded in07 is programmed to drive out07, no signal should be present. any signal that is present can be attributed to the other 15 hostile input signals because no other outputs are driven (they are all disabled). thus, this method measures the all-hostile input contribution to crosstalk into in07. of course, the method can be used for other input channels and combinations of hostile inputs. for output crosstalk measurement, a single input channel is driven (in00, for example) and all outputs other than a given output (in07 in the middle) are programmed to connect to in00. out07 is programmed to connect to in15 (far away from in00), which is terminated to ground. therefore, out07 should not have a signal present because it is listening to a quiet input. any signal measured at out07 can be attributed to the output crosstalk of the other 16 hostile outputs. again, this method can be modified to measure the other channels and the other crosspoint matrix combinations.
data sheet ADV3205 rev. 0 | page 19 of 20 effect of impedances on crosstalk the input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnitude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs do not have significant current flow to create magnetically induced cross- talk. however, significant current can flow through the input termination resistors and the loops that drive them. thus, the pcb on the input side can contribute to magnetically coupled crosstalk. from a circuit standpoint, the input crosstalk mechanism is similar to a capacitor coupling to a resistive load. for low frequencies, the magnitude of the crosstalk is given by | xt | = 20log 10 [( r s c m ) s ] where: r s is the source resistance. c m is the mutual capacitance between the test signal circuit and the selected circuit. s is the laplace transform variable. from the previous equation, it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. if the input is driven from a 75 terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. on the output side, the crosstalk can be reduced by driving a lighter load. although the ADV3205 is specified with excellent differential gain and phase when driving a standard 150 video load, the crosstalk is higher than the minimum obtainable due to the high output currents. these currents induce crosstalk via the mutual inductance of the output pins and bond wires of the ADV3205 . from a circuit standpoint, this output crosstalk mechanism is similar to a transformer with a mutual inductance between the windings that drives a load resistor. for low frequencies, the magnitude of the crosstalk is given by | xt | = 20log 10 ( mxy s/r l ) where: mxy is the mutual inductance of output x to output y. r l is the load resistance on the measured output. this crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing r l . the mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel lengths. pcb layout extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). the areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. the packaging of the ADV3205 is designed to keep the crosstalk to a minimum. each input is separated from every other input by an analog ground pin. directly connect all agnd pins to the ground plane of the circuit board. these ground pins provide shielding, low impedance return paths, and physical separation for the inputs. all of these help to reduce crosstalk. each output is separated from its two neighboring outputs by an analog supply pin of one polarity or the other. each of these analog supply pins provides power to the output stages of only the two nearest outputs. these supply pins provide shielding, physical separation, and a low impedance supply for the outputs. individual bypassing of each of these supply pins with a 0.1 f chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of shared common impedances. each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins. this technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the ic and in the package pins. directly connect these agnd pins to the ground plane. there are separate digital (logic) and analog supplies. dv cc must be at 5 v to be compatible with the 5 v cmos and ttl logic. av cc and av ee can range from 5 v to 12 v, depending on the application. locally decouple each power supply pin (or group of adjacent power supply pins) with a 0.1 f capacitor. use a 10 f capacitor to decouple power supplies as they come onto the board.
ADV3205 data sheet rev. 0 | page 20 of 20 outline dimensions compliant to jedec standards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 14.20 14.00 sq 13.80 16.20 16.00 sq 15.80 051706-a figure 31. 100-lead low profile quad flat package [lqfp] (st-100-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADV3205jstz 0c to 70c 100-lead low prof ile quad flat package [lqfp] st-100-1 ADV3205-evalz evaluation board 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10342-0-12/11(0)

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